000330.1 B N F. Burton Representation Call Frame extension


The stack frame for PowerPC with AltiVec support looks like:

    +-------------+ <--- Stack before prolog (Old SP)
    !  freg save  !
    !  greg save  !
    !  alignment  !
    !  vreg save  !
    !   locals    !
    !     ...     !
    !   Old SP    !
    +-------------+ <--- Stack after prolog (New SP)

Without AltiVec support the size of the "alignment" field is zero.
With AltiVec support the size of the "alignment" field is calculated
at runtime to 0 or 8 since the AltiVec registers loads and stores must
be aligned on 16 byte and the stack at function entry is aligned on 8.

I don't see any way to describe this with the current specification.
Please correct me if I am missing something...


- Add to section 6.4.2:

19. DW_CFA_def_cfa_expression takes one block argument encodes as
    DW_FORM_block. The required action is to define the current CFA
    rule to use the provided expression.

20. DW_CFA_expression takes two arguments: an unsigned LEB128 constant
    representing a register number and a block encoded as DW_FORM_block.
    The required action is to change the rule for the register indicated
    by the register number to use the expression to calculate its stack
    location. The value of the CFA is pushed on the evaluation
    stack prior to evaluating the expression.

- Add to figure 37:

    DW_CFA_def_cfa_expression     0      0x0f     BLOCK
    DW_CFA_expression              0      0x10     ULEB128 register BLOCK

- Change section 7.23:

The value of the CIE id in the CIE header is 0xffffffff. The initial value
of the CIE version number is 2.

- Add to section 6.4.1 page 61

expression(E) The previous value to this register is located at the
address produced by the expression.

- The above may replace the "architectural" entry.


main+0x0:      rlwinm     r12,r1,0,28,28
main+0x4:      addi       r11,r1,0
main+0x8:      mfspr      r0,lr
main+0xc:      subfic     r12,r12,-48
main+0x10:     stwux      r1,r1,r12
main+0x14:     stw         r31,-4(r11)
main+0x18:     stw        r0,4(r11)
main+0x1c:     addi       r0,r1,32
main+0x20:     bl          _savevr31
main+0x24:     vspltisw   v31,5
main+0x28:     addi       r31,r0,0
main+0x2c:     addis      r3,r0,.L5@ha
main+0x30:     addi       r3,r3,.L5@l
main+0x34:     addi       r4,r31,0
main+0x38:     vsldoi     v2,v31,v31,0
main+0x3c:     crxor      6,6,6
main+0x40:     bl          printf
main+0x44:     addi       r31,r31,1
main+0x48:     cmpi       0,0,r31,10
main+0x4c:     bc          12,0,main+0x2c
main+0x50:     addi       r3,r0,0
main+0x54:     lwz        r11,0(r1)
main+0x58:     addi       r0,r1,32
main+0x5c:     bl          _restvr31
main+0x60:     lwz        r0,4(r11)
main+0x64:     lwz         r31,-4(r11)
main+0x68:     mtspr      lr,r0
main+0x6c:     addi       r1,r11,0
main+0x70:     blr

            cie_end-cie-4      ; length
            0xffffffff              ; CIE_id
            2                       ; version
            0                       ; augmentation
            4                       ; code_alignment_factor
            -4                      ; data_alignment_factor
            108                     ; LR is the return address

            fde_end-fde-4      ; length
            cie                     ; CIE_ptr
            main                    ; initial_location
            0x70                    ; address_range
            DW_CFA_def_cfa_expression(DW_OP_breg1(0) DW_OP_deref)
            DW_CFA_expression(1155,DW_OP_const1s(-16) DW_OP_and
            DW_OP_const1u(48-32) DW_OP_minus)

Approved.  Extend CFA computation to make it more general. The PowerPC Altivec function prolog
dynamically aligns the stack by inserting alignment bytes. Current CFA only permits static description
of stack frame.  Add DW_CFA_def_cfa_expression and DW_CFA_expression to allow general
computation of arbitrary expression.

Modified:  CIE version number will remain 1.