|001113.1||A||M. Eager||Processor||Mulitple ISA Support|
Some computer architectures support multiple instruction formats.
For example, certain version of the ARM and MIPS microprocessors
support both a 32-bit instruction set as well as a different
16-bit instruction set. Current debuggers for these architectures
use various heuristics to determine how to interpret the ISA
to which a particular instruction belongs.
Section 6.2 describes the line number information for a program
as a matrix, with each row representing an instruction in the
program and a number of columns which contain a variety which
describes a number of different attributes. These attributes
include the address of the instruction, the source file, line
and column, and various other specifications. This matrix is
encoded as operations which modify a state machine which has
registers which represent the column values.
Add a column to the line number matrix to represent the ISA.
Add following to section 6.2.2, State Machine Registers:
isa A architecture-dependent encoding of the instruction
set architecture for this instruction. Initially
set to zero to represent the default ISA.
Add following to section 188.8.131.52, Standard Opcodes:
DW_LNS_incr_isa Increment the isa register value
DW_LNS_decr_isa Decrement the isa register value
For architectures which support only a single architecture,
no change is made to the line number table, so this scheme
is upward compatible and requires no change to current compilers
To support multiple ISA's, an architecture-dependent encoding
is used to specify the ISA. ISA zero is the default instruction
set. Changing to an alternate ISA is specified by including a
DW_LNS_incr_isa opcode; resuming the default ISA is specified
by including a DW_LNS_decr_isa opcode. In the unusual situation
where there are more than two ISA's supported, multiple opcodes
would be emitted.
This proposal adds an additional column in the line table to describe instruction set
two operators which increment or decrement this ISA specification value. It was adopted with the
following modification: a single operator DW_LNS_set_isa which takes an operand specifying an
ISA. The initial value of the ISA specification is the default ISA for the processor.