991108.1 W I M. Eager Processor Multiple instruction set support

Some processor architectures support multiple instruction sets.
For example, MIPS has both the standard 32-bit instructions and
the MIPS-16 instruction set. Other processors support completely
unrelated instruction sets.

A debugger needs to know the correct instruction set being used at a
given address to be able to disassemble instructions, or possibly
set breakpoints or perform other operations.

An AT_instruction_set attribute can be added to TAG_subroutine (and
others) which specifies the instruction set to be used in the function.
The values (0 to n) for this attribute would be architecture dependent.
Not specifying this attribute would be equivalent to specifying ISA 0.

This unfortunately does not address situations where the instruction
set may change within a function.

An alternative is to create a TAG_instruction_set which would be "owned"
by either a subroutine or a compilation unit. This would contain the
AT_instruction_set attribute as well as AT_low_pc and AT_high_pc attributes.
Multiple TAG_instruction_set DIEs could be specified.

I'm not aware of any existing Dwarf 2 extensions to support multiple ISAs.

This issue is resolved with 001113.1.